The present invention relates to a method of manufacturing a metal semiconductor field-effect transistor (MESFET) by controlling implanted peak surface dopants and, more particularly, to a method of manufacturing a MESFET having a high drain breakdown voltage by controlling implanted peak surface dopants.
Significant development has been made in FETs using compound semiconductors because of improvements in processing techniques. For example, for a MESFET using GaAs for a semi-insulating substrate, a low noise MESFET with a noise factor of 1.3 dB at a frequency of 12 GHz and a power MESFET with an output of 20 W at a frequency of 8 GHz are known. In such a MESFET, one means for improving element performance and reliability is an improvement in the main breakdown voltage. The drain breakdown voltage can be increased by rendering an ohmic contact layer (drain region) in a high-concentration layer.
The following conventional method produces a MESFET with a high drain breakdown voltage.
First, as shown in FIG. 1A, an n-type active layer 2 and an n.sup.+ -type layer 3 are sequentially formed on a GaAs semi-insulating substrate 1 by epitaxial growth. The n.sup.+ -type layer 3 formed in this manner has an electron concentration distribution as shown in FIG. 2. Then, as shown in FIG. 1B, mesa etching is selectively performed from the surface of the n.sup.+ -type layer 3 down to the interface with the substrate 1 so as to isolate the n.sup.+ -type layer 3 and the active layer 2 in an island form.
As shown in FIG. 1C, a resist pattern 4 as a lift-off material is formed by the photoengraving process (PEP) in a region including the surface of the island-shaped n.sup.+ -type layer. Subsequently, as shown in FIG. 1D, an AuGe layer 5 (5.sub.1 to 5.sub.5) and a Pt layer (not shown) are sequentially deposited on the entire surface including the resist pattern 4. During this step, the AuGe layers 5.sub.2 and 5.sub.4 and the Pt layers on the surface portion of the n.sup.3 -type layer 3, which is exposed through the resist pattern 4, are isolated from the AuGe layers 5.sub.1, 5.sub.3 and 5.sub.5 and the Pt layers on the resist pattern 4, by a step of the resist pattern 4.
As shown in FIG. 1E, the resist pattern 4 is removed to lift off the overlying AuGe layers 5.sub.1, 5.sub.3 and 5.sub.5, and the Pt layers, thereby forming source and drain electrodes 6 and 7 of Pt/AuGe on the surface of the n.sup.+ -type layer 3. Annealing is performed at 450.degree. C. to form ohmic contacts between the source and drain electrodes 6 and 7 and the n.sup.+ -type layer 3.
Referring to FIG. 1F, after forming, by PEP, a resist pattern 8 having an opening corresponding to a prospective gate region, the n.sup.+ -type layer 3 and the surface region of the active layer 2 are sequentially etched using the resist pattern 8 as a mask so as to form a recess 9. The recess 9 thus isolates: the two regions of the n.sup.+ -type layer 3; an n.sup.+ -type source region 10 which forms at its upper surface an ohmic contact with the source electrode 6; and an n.sup.+ -type drain region 11 which forms at its upper surface an ohmic contact with the drain electrode 7.
In the next step, as shown in FIG. 1G, an aluminum film 12 (12.sub.1 to 12.sub.3) is deposited on the entire surface of the structure including the resist pattern 8. Then, the aluminum film 12.sub.2 on the active layer 2 at the bottom surface of the recess 9, is isolated from the aluminum films 12.sub.1 and 12.sub.3 on the resist pattern 8, by the step between the resist pattern 8 and the recess 9. Finally, as shown in FIG. 1H the resist pattern 8 is removed to lift off the overlying aluminum films 12.sub.1 and 12.sub.3, and a gate electrode 13 of aluminum is formed on the active layer 2 to complete the MESFET.
The drain breakdown voltages of fifty MESFETs manufactured by the above-mentioned method were examined. As a result, a voltage distribution graph falling within the range of 40 to 45 V was obtained as shown in FIG. 3, indicating good drain breakdown voltage characteristics. The drain breakdown voltage was measured with measuring equipment as shown in FIG. 4. Measurements were made under the following conditions. While a negative bias was applied from a DC power source 22 to the gate electrode of a MESFET 21 through a resistor 23, a positive pulse from a pulse generator 24 with a duration of 0.1 .mu.s and a duty of 0.01% was applied to the drain electrode. The breakdown voltage of the MESFET was measured with an oscilloscope 25 connected to the drain electrode. The source electrode of the MESFET was grounded during the measurement.
The conventional manufacturing method wherein the n.sup.+ -type layer is formed by epitaxial growth has the following disadvantages. First, with an increase in the growth area of the n.sup.+ -type layer, electron concentration and the resultant film thickness tend to vary. This prevents the easy manufacture of MESFETs having a uniform performance. Second, materials such as gallium, arsenic trichloride (AsCl.sub.3) and the like are costly. Third, the availability of the epitaxial growth equipment limits the number of substrates on which n.sup.+ -type layers can be formed within a single step, thus preventing effective mass production.
In view of this, a method for manufacturing a MESFET has been proposed wherein an n.sup.+ -type ohmic contact layer (source, drain regions) is formed by ion implantation. This method will now be described with reference to FIGS. 5A to 5L.
A GaAs semi-insulating substrate 31 as shown in FIG. 5A is prepared. Then, as shown in FIG. 5B, a resist pattern 32 is formed by PEP on the major surface of the semi-insulating substrate 31. Using the resist pattern 32 as a mask, an impurity such as silicon is ion-implanted into the substrate 31 at an acceleration energy of 150 keV in a dose of 3.times.10.sup.12 cm.sup.-2 so as to form a silicon ion injection layer 33 for an active layer.
As shown in FIG. 5C, after the resist pattern 32 is removed, another resist pattern 34 is formed by PEP which has an opening corresponding to a prespective ohmic contact layer (source, drain regions). Using the resist pattern 34 as a mask, an impurity such as silicon is ion-implanted twice into the substrate 31 with the acceleration energies of 120 keV and 250 keV in a dose of 2.times.10.sup.13 cm.sup.-2. Thus, the silicon ion injection layers 35.sub.1 and 35.sub.2 for source and drain regions are formed. Subsequently, as shown in FIG. 5D, after the resist pattern 34 is removed, annealing is performed at 850.degree. C. for 15 minutes to activate the silicon ion injection layer 33, 35.sub.1 and 35.sub.2 of the semi-insulating substrate 31. Thus, an n-type active layer 36 having a depth of 0.25 .mu.m, and n.sup.+ -type source and drain regions 37 and 38 having a depth of 0.4 .mu.m are formed. The source and drain regions 37 and 38 formed in this manner have the electron concentration distribution as shown in FIG. 6.
Then, as shown in FIG. 5E, after depositing an SiO.sub.2 film 39 of 5,000 .ANG. thickness on the major surface of the semi-insulating substrate 31 by the plasma CVD (Chemical Vapor Deposition) method, a resist pattern 40 is formed by PEP which has openings corresponding to parts of the source and drain regions 37 and 38. Subsequently, as shown in FIG. 5F, using the resist pattern 40 as a mask, the SiO.sub.2 film 39 is selectively etched by, for example, dilute hydrofluoric acid to form openings 41.sub.1 and 41.sub.2. In this etching step, the SiO.sub.2 film 39 is over-etched and the resist pattern 40 is overhung.
In the next step shown in FIG. 5G, an AuGe layer 42 (42.sub.1 to 42.sub.5) and a Pt layer (not shown) are sequentially deposited on the entire surface including the resist pattern 40. The AuGe layers 42.sub.2 and 42.sub.4 and the Pt layers on the surfaces of the source and drain regions 37 and 38 in the openings 41.sub.1 and 41.sub.2, which are exposed through the resist pattern 40, are isolated from the AuGe layers 42.sub.1, 42.sub.3 and 42.sub.5 and the Pt layers on the resist pattern 40, by the step of the resist pattern 40 and the SiO.sub.2 film 39. The resist pattern 40 over hangs the openings 41.sub.1, 41.sub.2 of the SiO.sub.2 film 39. Therefore, the sides of the AuGe layers 42.sub.2, 42.sub.4 and Pt layers are at the distance corresponding to the length of the overhang from the surfaces of the openings 41.sub.1, 41.sub.2. Subsequently, as shown in FIG. 5H, the resist pattern 40 is removed to lift off the overlying AuGe layers 42.sub.1, 42.sub.3 and 42.sub.5 and the Pt layers, to form source and drain electrodes 43 and 44 of Pt/AuGe on most parts of the source and drain regions 37 and 38. Annealing is then performed at 450.degree. C. to form ohmic contacts between the source and drain electrodes 43 and 44, and the surfaces of the n.sup.+ -type source and drain regions 37 and 38, respectively.
As shown in FIG. 5I, a resist pattern 45 is formed by PEP which has an opening corresponding to a prospective gate region. Referring to FIG. 5J, using the resist pattern 45 as a mask, the SiO.sub.2 film 39 is selectively etched with, for example, dilute hydrofluoric acid to form a recess 46. During this etching step, the SiO.sub.2 film 39 is overetched and the resist pattern 45 is overhung.
Referring to FIG. 5k, an aluminum film 47 (47.sub.1 to 47.sub.3) of, for example, 4,000 .ANG. thickness is formed on the entire surface including the resist pattern 45. The aluminum film 47.sub.2 on the surface of the active layer 36 at the bottom surface of the recess 46, which is exposed through the resist pattern 45, is isolated from the aluminum films 47.sub.1 and 47.sub.3 on the resist pattern 45, by the step of the resist pattern 45 and the SiO.sub.2 film 39. The resist pattern 45 overhangs the recess 46 of the SiO.sub.2 film 39. Hence, the side of the aluminum film 47.sub.2 is at the distance corresponding to the length of the overhang from the surface of the recess 46. Finally, as shown in FIG. 5L, the resist pattern 45 is removed to lift off the overlying aluminum films 47.sub.1 and 47.sub.3. A gate electrode 48 of aluminum is formed on the active layer 36 to complete the MESFET.
The drain breakdown voltages of fifty MESFETs manufactured by the method adopting ion injection as described above were measured with measuring equipment similar to that shown in FIG. 4. The result, as shown in FIG. 7, was that a voltage distribution falling within a range of 25 to 30 V was obtained. This range is lower than that (40 to 45 V) of the MESFETs of FIG. 1H manufactured by epitaxial growth. This lower voltage distribution prevents practical use of the ion injection method despite its many advantages.
For the following reason, the MESFET of FIG. 5L has a low drain breakdown voltage. As may be understood by comparing the electron concentration distribution (FIG. 6) of the n.sup.+ -type source, drain regions of the MESFET which have been formed by ion-implantation with the electron concentration distribution (FIG. 2) of the n.sup.+ -type layer of the MESFET (FIG. 1H) which has been formed by epitaxial growth, the electron concentration of the surface regions of the source and drain regions is so low that the depletion layer may easily reach the drain electrode. Current may therefore concentrate in the depletion layer and then flow to the drain electrode. More specifically, when voltage is applied on the gate, source and drain electrodes to operate the MESFET, the depletion layer formed in the active layer below the gate electrode will be pulled to the drain electrode. This pull increases in proportion to the voltage applied on the surface region of the drain electrode. It follows that, if the surface region of the drain region has a high electron concentration, the drain region prevents the depletion layer from reaching the drain electrode. On the other hand, if the surface region of the drain region has a low electron concentration, the drain region fails to block the depletion layer even if a relatively low voltage is applied on the drain electrode. In this case, the depletion layer extends through the surface region of the drain region to the drain electrode and current accumulates in the drain electrode, thus breaking down the MESFET.